Timed state space exploration using POSETs

| This paper presents a new timing analysis algorithm for eecient state space exploration during the synthesis of timed circuits or the veriication of timed systems. The source of the computational complexity in the synthesis or veriication of a timed system is in nding the reachable timed state space. We introduce a new algorithm which utilizes geometric regions to represent the timed state space and partially ordered sets (POSETs) to minimize the number of regions necessary. This algorithm operates on spec-iications suuciently general to describe practical circuits, as well as other timed systems. The algorithm is applied to several examples showing signiicant improvement in run-time and memory usage.